A new open-source software package, CoreTML framework, has been just released. It provides the necessary tools to create configurable RTL IP cores that produce VHDL/Verilog source based on user-supplied parameters.

CoreTML framework is arguably the first such piece of software that is both open-source and vendor-neutral. Currently configurable IP cores provide their own ways for the user to set up core parameters. Commercial EDA suites for FPGA design come with vendor-locked tools that can be used to generate only the IP cores developed by the EDA vendor or its partners. Being liberally licensed, CoreTML framework doesn't impose such a limitation and can be used for both commercial and noncommercial projects while achieving maximum portability.

A configurable IP core includes a definition of its parameters and a set of templates which are used to generate RTL source code. CoreTML templates are based on a specially designed Template Markup Language that allows the developer to supplement VHDL/Verilog source code with additional control tags which are recognized by the processing software. Template Markup Language leverages Lua programming language to provide a flexibility needed for the design of configurable IP cores.

CoreTML includes a Temlpate Markup Language processing tool, a graphical tool that can be used to configure the IP core, a couple of IP core examples and full documentation. CoreTML framework is licensed under the terms of the GNU Lesser General Public License (LGPL).

The development team also plans to develop a few more IP core examples to make a small configurable IP core library based on the CoreTML framework, as well as to make EDA integration smoother.