Semiconductor IP core design
CoreTML was created primarily to serve as a framework for RTL (Register Transfer Level) IP core generator design and deployment. Although other approaches can be used for this purpose, CoreTML has several advantages:
- It is much more versatile than standard Verilog and VHDL language features;
- As opposed to general-purpose programming language, CoreTML reduces overhead and uses standard means to instantiate templates and pass parameters between them;
- TMLconf allows the developer to create configuration GUIs easily.
The following examples are included both into the source and binary ditributions of the CoreTML framework.
VHDL Hamming encoder/decoder IP core generator
- shortened and/or extended codes supported
- dual error detection
- can be used as a part of an iterative decoding scheme
FPGA memory IP core generator
- generic, Xilinx RAMB4 and Xilinx RAMB16 architectures
- single-port and dual-port memories
Low-pass filter generator
- generate low-pass FIR filter using windowed-sync method
- different window functions are supported
- number of multipliers is halved due to impulse response symmetry
- pipelined adder
CoreTML framework is not limited to generating files in any particular language; in fact, it can be used to generate any text files. Its architecture was designed to be as neutral as possible, so that it can have many applications.
Some software uses configuration files to store its settings. Sometimes only few settings can be configured via program's GUI, if any. Such a configuration GUI can be created fairly easily with the CoreTML framework.
Since a lot of business documents are similar and often created with "copy-paste" techinque, CoreTML can be used to generate such documents based on user-supplied parameters. The documents must be in some text-based format (e.g. RTF, TeX or HTML).
Copyright © 2010-2015 by Alex I. Kuznetsov.
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